A conventional computer system 100 includes a processor 102 coupled through a system bus 104 to a system memory 106 as illustrated in FIG. 1. The system memory 106 includes a memory controller 108 coupled to the system bus 104 and coupled to three memory modules 110A–C though a common data bus DQ, address bus ADDR, and control bus CONT. Each memory module 110A–C includes a plurality of individual memory devices 112, one of which is shown on the memory module 110A. Each of the memory devices 112 is typically a dynamic random access memory (DRAM) since DRAMs form the largest portion of system memory 106 because they provide large storage capacity at relatively inexpensive prices. In response to a request from the processor 102, the memory controller 108 initiates a memory operation by providing a memory command in the form of control signals and a memory address (generally in the form of a row address and a column address) on the control bus CONT and address bus ADDR, respectively, to all of the memory modules 110A–C. If the memory operation is a write operation, the memory controller 108 will also apply write data to the memory modules 110A–C through the data bus DQ. To prevent all of the memory modules 110A–C from responding to the memory command, the memory controller 108 also generally applies a unique chip select or similar select signal over the control bus CONT to each of the memory modules 110A–C so that only the memory module receiving an active chip select signal responds to the memory command. Each memory module 110A–C may receive more than one chip select signal, with each group of memory devices 112 receiving the same chip select signal being designated a “rank” of memory.
Conventional processors 102 generally operate at a relatively high speed compared to the memory modules 110A–C. Because access to system memory 106 is a frequent operation of the processor 102, the slower operating speed of the memory 110A–C greatly slows the overall operation of the computer system 100, as will be appreciated by those skilled in the art. As a result, much effort has been put into increasing the data transfer rate or bandwidth of the data bus DQ to enable system memory 106 to transfer data more quickly. To increase the bandwidth of the data bus DQ, the width of the data bus has been increased, and new types of DRAM technology having much higher transfer speeds, such as RAMBUS DRAMs (“RDRAMs”) and synchronous link DRAMs (“SLDRAMs”), have also been developed. As the operating speed of the data bus DQ increases, however, noise, signal skew, a smaller data eye—which defines the duration for which the data signals are valid—and other factors make it more difficult to reliably transfer data over the data bus.
One approach that has been utilized in transferring data more reliably at high data transfer rates is an adaptive process of adjusting the delay between data signals and a clock signal transmitted along with the data signals. A receiving device captures the data signals in response to the clock signal. The process involves applying the clock signal and a pseudorandom bit pattern having known values on the data bus DQ. The timing relationship or delay between the data signals forming the pseudorandom bit pattern and the clock signal is thereafter adjusted through a series of values, and the bit pattern captured at each value of the delay. Because the pseudorandom bit pattern has known values, the captured data can be compared to the expected values to determine whether the bit pattern was successfully captured at each value of the delay between the bit pattern and the clock signal. The values for the delay between the bit pattern and the clock signal where the bit pattern was unsuccessfully captured are designated failing values, and the values where the bit pattern was successfully captured are designated passing values. The range of the passing values define the data eye of the applied bit pattern, and a final value of the delay between the bit pattern and the clock signal may be selected in the middle of the data eye to optimize the delay for successful capture of the bit pattern. This approach is described in more detail in U.S. Pat. No. 6,338,127 to Manning entitled METHOD AND APPARATUS FOR RESYNCHRONIZING A PLURALITY OF CLOCK SIGNALS USED TO LATCH RESPECTIVE DIGITAL SIGNALS, AND MEMORY DEVICE USING SAME, and in U.S. Pat. No. 6,374,360 to Keeth et al. entitled METHOD AND APPARATUS FOR BIT-TO-BIT TIMING CORRECTION OF A HIGH SPEED MEMORY BUS, both of which are incorporated herein by reference.
In addition to systems communicating via electrical signals, such as the RDRAM and SLDRAM technologies mentioned above, optically-based memory systems including an optical communications link between the memory controller 108 and memory modules 110A-C have also been developed to increase the bandwidth of system memory 106. In such optically-based systems, however, problems of transmitting and receiving optical signals between the memory controller 108 and the memory modules 110A-C result in unacceptably high bit error rates (BER) and continue to hamper the commercialization of such systems, particularly in system memories 106 having parallel, closely-spaced memory modules of the type found in many existing personal computer systems. For example, in an optically-based system the optical transmitter and receiver must be designed to have sufficient dynamic range to accommodate all possible variations in system memory parameters such as the total number of memory modules. Dynamic range defines the required operating range of a parameter of the receiver or transmitter, such as required power of a received optical signal for a receiver, as will be understood by those skilled in the art. Sufficient dynamic range is required to ensure optical signals are reliably transmitted and received, and transmitters and receivers having larger dynamic range are more costly, increasing the overall cost of optically-based memory systems.
There is a need for a system memory that reliably transfers data at a high bandwidth but has a relatively low cost for use in computer systems and other cost-sensitive applications.